Machine Learning–Based Power Consumption Prediction for Logic Circuits

Abstract

Due to growing circuit complexity and the need for energy-efficient operation, power con- sumption has emerged as a crucial design constraint for contemporary digital systems. Tra- ditional analytical and simulation based power estimation methodologies often suffer from limited scalability and high computational cost when applied to large logic architectures. This research proposes a machine learning-based framework for predicting the dynamic power consumption of logic circuits using readily available circuit-level parameters. A synthetic dataset is generated using logic-level power modeling by varying switching activity, load capacitance, supply voltage, operating frequency, and gate count. Supervised regression models including Linear Regression, Support Vector Regression, and Random For- est Regression are trained and evaluated using Mean Absolute Error, Root Mean Square Error, and coefficient of determination. Unlike prior approaches that rely on post-layout or technology-dependent parameters, the proposed framework focuses on early-stage, technology-neutral power estimation. Experi- mental results demonstrate that ensemble learning significantly improves prediction accuracy while reducing estimation complexity. Although the study uses synthetic data, the frame- work provides a scalable foundation for early-stage power-aware logic circuit design and can be extended to real circuit benchmarks in future work..